About Me
Suhail Basalama has a Ph.D. in Computer Science from the University of California, Los Angeles, working in the VLSI Architecture, Synthesis, and Technology (VAST) Lab. His research focuses on automating the translation of AI models into dataflow and systolic hardware accelerators using design-space exploration (DSE) and compiler techniques. He has developed novel methodologies, compilers, and frameworks for optimizing systolic arrays, spatial accelerators, and dataflow architectures.
- AI HW/SW Co-Design
- Dataflow & Systolic Architectures
- AI Hardware Compilers
- AI-HW Design Space Exploration
- Performance & System Modeling
- Hardware Compilation & Synthesis
- Domain-Specific Computing
- EDA & VLSI Design Methodologies
Ph.D. in Computer Science
University of California, Los Angeles
M.S. in Computer Science
University of California, Los Angeles
B.S. in Computer Engineering
University of Arkansas
B.A. in Political Science
University of Arkansas
I’m a Ph.D. researcher at UCLA’s VAST Lab, focused on automating the translation of AI models into dataflow and systolic hardware accelerators using design-space exploration (DSE) and compiler techniques. My work spans hardware-software co-design, high-level synthesis, and efficient accelerator architectures for ML workloads. I build hardware compilers, frameworks, and design space exploration tools for automating ML hardware acceleration on FPGAs and ASICs.
Always happy to discuss research, exchange ideas, or collaborate! 😊
