Suhail Basalama
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    • Automating Hardware Acceleration of Deep Neural Networks using Dataflow Architectures
    • Dataflow Accelerators for DNNs using High-Level Synthesis
    • Dataflow Hardware Acceleration of DNNs with High-Level Synthesis
    • End-to-End CNN Acceleration and Systolic Array Design Space Exploration for FPGAs
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    • NoH: NoC Compilation in High-Level Synthesis
    • Stream-HLS: Towards Automatic Dataflow Acceleration
    • TAPA-CS: Enabling Scalable Accelerator Design on Distributed HBM-FPGAs
    • A Comprehensive Automated Exploration Framework for Systolic Array Designs
    • FlexCNN: An end-to-end framework for composing CNN accelerators on FPGA
    • Callipepla: Stream Centric Instruction Set and Mixed Precision for Accelerating Conjugate Gradient Solver
    • A Versatile Systolic Array for Transposed and Dilated Convolution on FPGA
    • A Customizable Domain-Specific Memory-Centric FPGA Overlay for Machine Learning Applications
    • SPAR-2: A SIMD Processor Array for Machine Learning in IoT Devices
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End-to-End CNN Acceleration and Systolic Array Design Space Exploration for FPGAs

Jul 1, 2024·
Suhail Basalama
Suhail Basalama
· 1 min read
Video
Date
Jul 1, 2024 12:00 AM — 12:00 AM
Event
Member Talk at SpatialML

End-to-End CNN Acceleration and Systolic Array Design Space Exploration for FPGAs — Member Talk at SpatialML (July 2024)

Last updated on Jul 1, 2024
Suhail Basalama
Authors
Suhail Basalama
Ph.D.
← Dataflow Hardware Acceleration of DNNs with High-Level Synthesis Sep 30, 2025

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